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The paper reports the preparation of two types of 2D rod-like nano-hydroxyapatite (nHA) (unmodified and modified) of varying high-aspect ratios, by modified co-precipitation method, without any templates. These both nHA were succe...
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The paper reports the preparation of two types of 2D rod-like nano-hydroxyapatite (nHA) (unmodified and modified) of varying high-aspect ratios, by modified co-precipitation method, without any templates. These both nHA were successfully introduced into novel synthesized Thermoplastic Polyurethane (TPU) matrices based on polycarbonate soft segments, by in-situ techniques. These nanocomposites were characterized and tested by Attenuated Total Reflection-Fourier Transform Infrared Spectroscopy, Wide Angle X-Ray Diffraction (WAXD), High Resolution Transmission Electron Microscopy (HRTEM), mechanical and and thermogravimetry analysis. Physico-mechanical properties of the in-situ prepared TPU/nHA nanocomposites were found to be superior compared to the pristine TPU. Thermal stability of the nanocomposites was improved tremendously. The polymer-filler interaction was reflected in the improved mechanical and thermal properties which were the consequences of proper dispersion of the filler in the polymer matrix. Improved biocompatibility of the prepared nanocomposites was confirmed by MTT assays using osteoblast-like MG63 cells. Prothrombin time (PT) and activated partial thromboplastin time (APTT), as calculated from coagulation assays, displayed an increase in the clotting time, particularly for the PPG wrapped (modified nHA) nanocomposites, prepared through the in-situ technique. Only 0.3% of hemolysis was observed for the in-situ prepared nanocomposites, which establishes the antithrombotic property of the material. The key parameters for enhancing the technical properties and biocompatibility of the nanocomposites are: the interfacial adhesion parameter (B_(σy)), the polymer-filler affinity, the aspect ratio of filler and non-covalent modifications, and the state of dispersion. Thus, the novel TPU/nHA nanocomposites have great potential for biomedical applications, in particular for vascular prostheses, cardiovascular implants, scaffolds, and soft and hard tissues implants.
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This work presents a testing scheme for Finite State Machines (FSM) based on Deep Neural Network (DNN). This technique determines whether a given implementation FSM-B is equivalent to its specification FSM-A. The input/output sequ...
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This work presents a testing scheme for Finite State Machines (FSM) based on Deep Neural Network (DNN). This technique determines whether a given implementation FSM-B is equivalent to its specification FSM-A. The input/output sequences (I/O pairs) for a given FSM train the proposed DNN. First, I/O pairs of FSM-A are generated using an adaptive distinguishing algorithm, and most of these sequences (around 80%) are used for training the DNN. After training, the remaining 20% I/O pairs are used for validating the derived DNN. After training and validation, the correctness of FSM-B is checked. A small number of vectors is applied to FSM-B and the generated outputs are compared with the DNN predicted outputs. Based on the similarity percentage between them, FSM-B is declared either as correct or faulty implementation of FSM-A. To check the effectiveness of the scheme, transfer-type faults are injected to construct mutant FSMs. The results of experimentation performed on the MCNC FSM benchmark prove the efficacy of this scheme. As only a subset of tests is needed to check the presence of fault if any, the testing time is remarkably less-resulting in an average reduction of 87.68% compared to the conventional technique. To the best of our knowledge, this DNN based testing scheme is being presented for the first time.
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For Network-on-Chip (NoC) latency estimation, current analytical models do not provide reliable results. As a result, they cannot be used for optimization of design space exploration. In this paper, we propose a DNN-based learning...
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For Network-on-Chip (NoC) latency estimation, current analytical models do not provide reliable results. As a result, they cannot be used for optimization of design space exploration. In this paper, we propose a DNN-based learning model for predicting the latency of a 3D fully connected NoC. The features needed for the DNN model are gathered from both the analytical model and from the Booksim simulator. The resulting DNN model has been applied to the mapping optimization loop for predicting the best mapping in conjunction with the parameters of an application and the NoC. In both synthetic and application-specific traffic simulations, we have found that using our proposed DNN model, prediction error is less than 8%. Furthermore, the mapping optimization using a prediction model predicts better solutions than the mapping optimization using communication cost.
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Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of sev...
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Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.
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Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of sev...
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Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.
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Network Routers find most defined path for an arriving packet by the destination address in the packet using longest prefix matching (LPM) with Routing table entries. In this paper we propose a new Ternary Content Addressable Memo...
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Network Routers find most defined path for an arriving packet by the destination address in the packet using longest prefix matching (LPM) with Routing table entries. In this paper we propose a new Ternary Content Addressable Memory (TCAM) based system architecture for the LPM problem in routers. The proposed architecture eliminates sorting of table entries during table update [1][2]. It also eliminates the priority encoder needed to find the longest prefix match in conventional techniques. This has advantage in large capacity routing tables as proposed technique uses a priority encoder only of size equal to the number of bits in destination address to find the longest prefix length. To implement the proposed method for LPM, TCAM cell is modified by including two control transistors which control connection of cell either with Bit Match Line (BML) or with Word Match Line (WML). Functionality of modified cell is verified by simulating 32-bit TCAM word in UMC 180 nm technology in Spectre. Difference in search cycle time has been observed to be comparable to the conventional TCAM. The proposed technique completely reduces the LPM problem to only three search cycles in proposed TCAM memory architecture. As in recent times router table update rate has increased along with its capacity, proposed architecture is expected to be advantageous over conventional in large capacity and high update rate routing tables, due to elimination of sorting [2] and storage of any extra information on new entry [3].
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Network Routers find most defined path for an arriving packet by the destination address in the packet using longest prefix matching (LPM) with Routing table entries. In this paper we propose a new Ternary Content Addressable Memo...
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Network Routers find most defined path for an arriving packet by the destination address in the packet using longest prefix matching (LPM) with Routing table entries. In this paper we propose a new Ternary Content Addressable Memory (TCAM) based system architecture for the LPM problem in routers. The proposed architecture eliminates sorting of table entries during table update [1][2]. It also eliminates the priority encoder needed to find the longest prefix match in conventional techniques. This has advantage in large capacity routing tables as proposed technique uses a priority encoder only of size equal to the number of bits in destination address to find the longest prefix length. To implement the proposed method for LPM, TCAM cell is modified by including two control transistors which control connection of cell either with Bit Match Line (BML) or with Word Match Line (WML). Functionality of modified cell is verified by simulating 32-bit TCAM word in UMC 180 nm technology in Spectre. Difference in search cycle time has been observed to be comparable to the conventional TCAM. The proposed technique completely reduces the LPM problem to only three search cycles in proposed TCAM memory architecture. As in recent times router table update rate has increased along with its capacity, proposed architecture is expected to be advantageous over conventional in large capacity and high update rate routing tables, due to elimination of sorting [2] and storage of any extra information on new entry [3].
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This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design for core based SOCs. Core testing solutions are generated as a set of wrapper configurations, represented as rectangles ...
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This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design for core based SOCs. Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC’02 benchmark SOCs shows that the proposed method provides better solutions compared to the recent works reported in the literature.
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This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design for core based SOCs. Core testing solutions are generated as a set of wrapper configurations, represented as rectangles ...
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This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design for core based SOCs. Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC'02 benchmark SOCs shows that the proposed method provides better solutions compared to the recent works reported in the literature.
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1 Introduction Congestive heart failure (CHF) has become very common type of disease observed among infant to old persons. It is a chronic progressive condition and affects the pumping power of muscles of heart. It refers to the s...
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1 Introduction Congestive heart failure (CHF) has become very common type of disease observed among infant to old persons. It is a chronic progressive condition and affects the pumping power of muscles of heart. It refers to the situation when fluid builds up around the heart causing the pump inefficiently. Most common types of CHF is Left-sided CHF when left ventricle doesn't properly pump blood out to body and as a result fluid can build up in lungs, causing breathing difficult. Left-sided CHF is divided into two categories: Systolic heart failure and Diastolic failure. Causes of CHF are mainly hypertension, Coronary artery disease, Bad Valve conditions, other conditions like diabetes, thyroid disease, and obesity, etc. First stage symptoms of CHF are fatigue, swelling, weight gain, increased need for urinate. Second stage symptoms of CHF are irregular heartbeat, cough developing from lungs, wheezing, shortness of breath, etc. last stage or severe symptoms of CHF are chest pain in upper body, rapid breathing, blue skin, fainting, etc. it may be noted that Chest pain radiating through upper body may be an indication of a heart attack. For heart failure in children and infants, symptoms are poor feeding, excessive sweating, difficulty breathing, etc. CHF diagnosis is normally done by electrocardiogram, echocardiogram, MRI, Stress tests, Blood tests, Cardiac catheterization.
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